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EX-0007
ST0004Execution

Trigger Single Event Upset

Description

The attacker induces or opportunistically exploits a single-event upset (SEU), a transient bit flip or latch disturbance in logic or memory, so that software executes in a state advantageous to the attack. SEUs arise when charge is deposited at sensitive nodes by energetic particles or intense electromagnetic stimuli. An actor may time operations to coincide with natural radiation peaks or use artificial means from close range. Outcomes include corrupted stacks or tables, altered branch conditions, flipped configuration bits in FPGAs or controllers, and transient faults that push autonomy/FDIR into recovery modes with broader command acceptance. SEU exploitation is probabilistic; the technique couples repeated stimulation with careful observation of mode transitions, watchdogs, and error counters to land the system in a desired but nominal-looking state from which other actions can proceed.

Mappings

ENISA controls

  • ENISA-STL-2025-03-sD.25-i10
    addresses
    moderate

    Integrity checks (ECC, software/firmware validation) detect transient bit flips that EX-0007 attempts to convert into persistent compromise.

  • ENISA-STL-2025-03-sD.29-i06
    addresses
    moderate

    Critical-telemetry-points monitoring including command counters and error counters surfaces the SEU rate and watchdog/error patterns that signal EX-0007 stimulation.

Cross-reference controls

SPARTA countermeasures

Cite as SafeMode Space, EX-0007 (SPARTA v3.2).

Built 2026-07-25 from 216 techniques, 334 regulation articles, 125 ENISA controls, 2,610 framework controls, and 90 countermeasures.